The present invention relates to a nonvolatile memory cell and a logic element device that use a ferroelectric layer.
Nonvolatile memories have become indispensable devices in conjunction with the recent miniaturization of devices and advances in portable devices. Flash memories and ferroelectric memories (FRAM) are nonvolatile memories that have already made their way into the market. In particular, miniaturized nonvolatile memories capable of high-speed operation have been proposed that use ferroelectrics for a portion of the insulating film, such as the gate insulating film, of a MISFET (metal insulator semiconductor field effect transistor). MISFETs using such a ferroelectric layer include MFISFETs using electrodes (M), ferroelectric layers (F), insulating layers (I) made from a regular dielectric material and Si substrates (S), and MFMISFETs using upper electrodes (M), ferroelectrics (F), middle electrodes (M), and gate insulating films (I) made of a regular dielectric material. In the present specification, these are referred to generically as MFS-type FETs.
In MFS-type FETs, the polarization of the ferroelectric is changed by applying a voltage of at least the coercive voltage of the ferroelectric, between the semiconductor substrate and the electrode sandwiching the ferroelectric layer, and the remanent polarization that remains in the ferroelectric after the removal of voltage puts the MISFET into a normal ON or a normal OFF state, which is stored as the information “0” or “1.” Using these polarization holding properties of ferroelectrics, MFS-type FETs are being studied for applicability as elements that require non-volatility and that are used as the nodes of memories or FPGAs, for example.
One example of an MFS-type FET is disclosed in JP 2000-138351A, in which a device has been proposed that includes two ferroelectric capacitors that are connected to the gate electrode of a field effect transistor.
On the other hand, in general, functional elements such as inverters (INV) and flip flops (FF) are used widely as semiconductor circuit elements.
FIG. 12 is an electric circuit diagram showing the configuration of an ordinary inverter circuit. FIG. 13 is a cross-sectional view showing the structure of a CMOS device configuring an ordinary inverter circuit.
As shown in FIG. 12 and FIG. 13, an ordinary inverter circuit includes an n-channel MISFET (nMISFET) and a p-channel MISFET (pMISFET) arranged in series between the terminal supplying power source voltage VDD and the terminal supplying ground voltage Vss. Moreover, it is configured such that an input signal Sin is input to the gate electrodes of the nMISFET and the pMISFET, and an output signal Sout is output from the source and drain regions of the nMISFET and pMISFET.
As shown in FIG. 13, a semiconductor substrate 101 that has been doped with p-type impurities is provided with an n-well 102. The nMISFET is disposed in the p-type region, whereas the pMISFET is disposed in the n-well 102. The nMISFET is provided with a gate insulating film 105 made of SiO2, a gate electrode 106 provided on the gate insulating film 105, and source and drain regions 103a and 103b that are formed at both sides of the gate electrode 106 within the Si substrate 101. The pMISFET is provided with a gate insulating film 107 made of SiO2, a gate electrode 108 formed on the gate insulating film 107, and source and drain regions 104a and 104b that are formed at both sides of the gate electrode 108 within the n-well 102. Additionally, a node 111, which is on the source region 103a of the nMISFET, receives the ground voltage Vss, and a node 112, which is on the source region 104b of the pMISFET, receives the power source voltage VDD. Moreover, the input signal Sin is inputted into the gate electrodes 105 and 108 of the MISFETs, and the output signal Sout is outputted from a node 113, which is provided spanning between the drain region 103b of the nMISFET and the drain region 104a of the pMISFET.
FIG. 14 is an equivalent circuit diagram showing the configuration of an ordinary flip-flop circuit. As shown in the diagram, a flip-flop FF is configured by the combination of numerous nMISFETs and pMISFETs, and has the function of holding input data. As such, flip-flops FF have numerous applications, for example, they are used as the basic cells of SRAMs.
However, to store data, FFs include portions in which inverters are connected in series and to apply feedback, and moreover FFs are volatile, so that the stored data is erased when the power source is removed.
As a countermeasure, as disclosed in JP H05-250881A and JP 2000-77986A, for example, a non-volatile flip-flop circuit has been proposed in which an MFS-type element is used instead of the MISFETs in the flip-flop circuit, in order to remedy volatility.
The above-mentioned conventional technologies, however, have encountered the following problems.
Conventional MFS-type FETs have an insulating layer I, which is made of a regular dielectric material, and a ferroelectric layer F, deposited in that order. Therefore, when voltage is applied to the gate electrode to reverse the polarization of the ferroelectric layer F, the applied voltage is distributed between the ferroelectric layer F and the insulating layer I, with the amount of distribution of voltage to the ferroelectric layer F being determined by the ratio of the capacitance Ci of the insulating layer I to the capacitance Cf of the ferroelectric layer F.
This means, to generate a reversal in polarization of the ferroelectric layer F, it is necessary to make the capacity Cf of the ferroelectric layer F small. However, charge must be induced that generates a threshold shift in the insulating layer I depending on the polarization of the ferroelectric layer F, so that physical values such as the remanent polarization of the ferroelectric material, physical values such as the induction rate and the film thickness of the insulating material, as well as the ratio of the area of the insulating layer I to the ferroelectric layer F, and the thickness of the ferroelectric layer F are adjusted. In MFISFETs, however, voltage is applied for creating polarization between the semiconductor substrate and the gate electrode, so depending on the structure of the semiconductor substrate, structural or operational problems may occur, such as a depletion layer becoming sandwiched between the portion of the semiconductor substrate to which voltage is applied and the gate electrode, or the total capacity being easily affected by the potential of the source region and the drain region.
FIG. 11 is a graph showing the results of a simulation of the drain current Id as a function of the gate voltage Vg of an MFS-type FET taking the area ratio AR (=area of the insulation layer I/area of the ferroelectric layer F) as a parameter. As shown in the graph, when a large area ratio AR is taken to increase the amount of voltage distributed to the ferroelectric layer F, it can be seen that the saturation drain current decreases. That is, because the insulating layer I and the ferroelectric layer F being used are arranged in series, the total capacity between the gate electrode and the semiconductor substrate is reduced, and in comparison to a case in which the gate insulating film is made up of only the insulating layer I, the saturation drain current is reduced. Consequently, in order to secure sufficient saturation drain current it is necessary to increase the size of the FET.
On the other hand, when writing to an MFS-type FET, the voltage that is required to reverse the polarization between the gate electrode and the semiconductor substrate is applied, and when reading out from an MFS-type FET, a voltage not higher than the writing voltage is applied between the gate electrode and the semiconductor substrate. When reading out, even if the voltage applied to the ferroelectric layer F is not higher than the coercive voltage, a portion of the polarization becomes reversed due to the a minor hysteresis loop of the ferroelectric. This phenomenon is called read disturb, and when multiple read-outs are repeated, the ability to obtain the threshold shift necessary for a read-out is lost.
Among MFS-type FETs, with MFISFETs and MFMISFETs, operations such as reading out while writing were difficult because the same gate electrode is used for reading out and writing.
Furthermore, the MFMISFET mentioned in JP 2001-38351A is made of two ferroelectric capacitors connected in parallel to the gate electrode of a MISFET, so to generate a potential in the gate electrode necessary for a threshold shift, it is necessary to intricately adjust the size of the ferroelectric capacitors and the film thickness of the ferroelectric, and there are processing difficulties and problems in the reduction of the cell area. Additionally, during the read-out, a voltage is applied to only one of the two ferroelectric capacitors arranged in parallel, so although read disturb is reduced, in terms of percentage it is reduced to only half. Also, operations such as writing to the ferroelectric layer F while reading out information cannot be achieved.
On the other hand, the flip-flop circuit disclosed in JP H05-250881 simply replaces the MISFETs of an ordinary flip-flop circuit with MFS-type FETs, and the flip-flop circuit disclosed in JP 2000-77986A simply replaces the MISFETs of an ordinary master-slave flip-flop with MFS-type FETs. Consequently, these proposals require the same number of FETs as normal flip-flop circuits, and have the problem that it is necessary to change the writing voltage, and that the scale of the circuit increases.